Technical Field
The present disclosure generally relates to high speed integrated circuits, and in particular, to the use of ferroelectric capacitors to improve performance of DRAM memory cells.
Description of the Related Art
Transistor devices are coupled together by multi-layer metal interconnect structures to form integrated circuits (ICs) such as logic devices, or processors, and random access memory arrays such as static RAM (SRAM), dynamic RAM (DRAM), and flash memory. As the dimensions of integrated circuit elements continue to shrink below 20 nm, integration of new materials within the interconnect structures becomes more challenging. Materials used to form the interconnect structure at the 20 nm technology node include various metals and ultra-low-k (ULK) dielectrics that provide insulation between stacked metal layers, and between adjacent metal lines. To achieve fast device operation, it is important that vertical capacitances between the metal layers and horizontal capacitances between the metal lines are minimized. While it is desirable to reduce the vertical capacitances as much as possible by using ULK dielectrics, such materials tend to be porous and lack structural integrity, as is described in U.S. patent application Ser. Nos. 14/098,286 and 14/098,346 to the same inventor as the inventor of this patent application. While device speeds benefit from small capacitances, DRAMs and other high speed, high density memories under development require larger capacitances for increased storage capacity, and low power operation. Thus a conflict arises, for memory ICs in particular, between the need for higher speed and larger storage capacity.
As is well known in the art, conventional dielectric capacitors include two conducting plates separated by a dielectric material such as, for example, silicon dioxide (SiO2). When a voltage is applied across the plates, dipole moments within the dielectric material align to produce an internal polarization P that opposes the electric field E associated with the applied voltage, thus allowing positive charge to remain on one metal plate and negative charge to remain on the other conducting plate, as stored charge. The amount of charge stored on the plates is proportional to the applied voltage, according to the linear relationship Q=CV. The constant of proportionality, C, is known as capacitance, which is a positive value. A conventional capacitor has a fixed capacitance that is independent of the circuit in which it is used. Furthermore, the relationship between the polarization P and the applied electric field E is also linear.
There also exist ferroelectric capacitors in which a ferroelectric material is substituted for the dielectric material between the conducting plates. Behavior of ferroelectric capacitors for use in nanoscale devices is described by Salahuddin and Datta (Nano Letters, Vol. 8, No. 2, pp. 405-410). At certain temperatures, ferroelectric materials exhibit spontaneous polarization P that can be reversed by applying an electric field. Materials that have ferroelectric properties at, or close to, room temperature include, for example, barium titanate (BaTiO3), lead titanate (PbTiO3), and lead zirconate titanate (PZT). In analogy with ferromagnetic materials, the relationship between the polarization P and the applied electric field E of a ferroelectric capacitor exhibits hysteresis and is therefore non-linear. Furthermore, there can be a region of the associated hysteresis curve in which the slope dP/dE is negative and the capacitor is unstable. Normally, the induced polarization opposes the applied electric field. However, during an intermittent time interval during which the slope of the hysteresis curve is negative, the induced polarization enhances the applied field, thus creating positive feedback.
Because the ferroelectric material is already polarized before a voltage is even applied, the charge stored in the ferroelectric capacitor is not zero when V=0. Instead, the relationship between the stored charge and the capacitance is given byQ=Co(V+αQ).  (1)In Equation (1) αQ is a feedback voltage that is proportional to the charge Q on the capacitor, wherein a is α constant of proportionality. The effective capacitance Ceff that satisfies the relationship Q=CeffV is then given by Ceff=Co/(1−αCo), which theoretically can be a negative number when α Co>1. Negative values of Ceff are associated with the unstable region of the hysteresis curve and are unlikely to be observed experimentally.